The present invention relates to frequency synthesizers and more particularly to a fractional division frequency synthesizer of the indirect synthesis type.
Frequency synthesizers fall into two general classes. The first class is a direct frequency synthesis where new frequencies are derived from a single reference frequency by means of combinations of several additions, subtractions, multiplications and divisions of the reference frequency. This method is very complex and such a synthesizer is very expensive requiring a large number of passive and active elements.
A second class of synthesizer employs indirect frequency synthesis wherein new frequencies are derived from a single reference frequency by means of programmable phase-lock loops which contain whole number frequency dividers. If small steps in output frequency are necessary, then several phase-lock loops are employed, the output of one loop being divided and then added to or subtracted from the next. In other words, the output frequency of the synthesizer is divided down to the lower frequency for phase comparison with a reference frequency. A digital divider with an integer divisor provides an output frequency resolution which is directly related to the reference frequency. As higher resolution is needed, the reference frequency must be lowered. With a lower reference frequency, the short-term stability decreases and the phase-noise increases.
When short-term stability must be high and phase-noise low, a complex, multiple phase-lock loop system must be employed. Unfortunately, such multiple-loop, prior art synthesizers are expensive and complicated and it is very difficult to control spurious signals which may occur at many different frequencies, both close to or far away from the carrier frequency.
The problem, then, is to provide a frequency synthesizer which does not suffer from the above-mentioned defects. This problem has been solved by the frequency synthesizer disclosed in U.S. Pat. No. 3,959,737 of W. J. Tanis, one of the inventors of the instant application, the disclosure thereof being incorporated herein by reference. In the synthesizer of the above-identified Patent the digital divider in the phase-locked loop is effectively made to divide in fractional steps so that a much higher reference frequency may be employed than used in the prior art systems. This permits the use of only one main phase-locked loop, in the aforementioned synthesizer or section thereof, thus holding generation of spurious signals to a minimum. A secondary loop, used for the fractional dividing, does produce some close-to-the-carrier spurious signals, but if unacceptable this is effectively reduced by means of a tuneable frequency discriminator, or a sideband reduction ramp generator or a combination of both.
The frequency synthesizer of the above-identified U.S. Patent includes a voltage-tuned oscillator, the output frequency of which is proportional to a DC (direct current) potential applied to the tuning port thereof. The synthesizer also includes a digital divider connected to the output of the voltage-tuned oscillator, the digital divider dividing the output frequency of the voltage-tuned oscillator by a factor of N, where N is an integer or fractional number greater than one. The circuit includes means, connected to the digital divider, for altering the value of the factor N and a source of a reference frequency signal. Means, connected to the output of the digital divider and to the source of the reference signal, to compare the phase of the reference frequency signal with a phase of the divided output of the voltage-tuned oscillator thereby generating an error signal if there is any phase difference detected. The synthesizer also includes means for supplying the error voltage to the tuning port of the voltage-tuned oscillator whereby the oscillator alters its output frequency, and hence the output frequency of the synthesizer, in an offsetting manner to reduce the error signal towards zero. The operation of the fractional divider produces an unwanted, low-frequency ramp signal which is super-imposed upon the correction signal when there is a phase difference between the reference signal and the divided output signal of the voltage-tuned oscillator. It is this ramp signal that tends to produce spurious sidebands in the RF (radio frequency) output signal from the synthesizer. To eliminate this problem, the synthesizer further includes a sideband reduction circuit which is connected to the output of the fractional divider and to an intermediate output thereof. The output of the sideband reduction circuit is connected to the second input of a summing amplifier. The sideband reduction circuit reduces the effect of the unwanted ramp signal by providing a nulling ramp signal of opposite phase. The sideband reduction circuit and removal of the unwanted ramp signal is accomplished using analog techniques.
Variations of the frequency synthesizer of the above-identified U.S. Patent all have used an analog correction ramp and analog summing.